The present invention relates to integrated circuit fabrication, and more specifically to a polishing apparatus and to a method for polishing a layer of material in an integrated circuit.
Polishing processes, and more specifically chemical-mechanical polishing processes, have been used in the semiconductor industry to prepare both single crystal substrates and silicon on insulator substrates. In addition, chemical-mechanical polishing processes have also been used to planarize various conductive and insulating layers subsequently deposited on these substrates, during the integrated circuit fabrication process. For example, chemical mechanical polishing has been used to planarize interlevel dielectric layers that lie in between two different levels of metal interconnect. Planarizing the interlevel dielectric layer, prior to the formation of the next level of interconnect, is highly desirable because it allows the next level of interconnect to be subsequently patterned and etched without the formation of conductive metal stringers, which can electrically short adjacent metal lines, and without the formation of thinned or notched metal lines, which can adversely effect device reliability. Similarly, chemical-mechanical polishing has been used to planarize conductive materials, such as tungsten, copper, and aluminum, to form planar contact plugs, via plugs, and interconnects. In addition, chemical-mechanical polishing has also been used to form trench isolation. In this process, trenches are formed and then subsequently filled with a deposited dielectric layer, such as silicon dioxide. The dielectric layer is then polished back to form dielectric filled isolation trenches, which are nearly planar with the adjacent active regions. In addition to being planar, the resulting trench isolation is also desirable because it allows the space separating adjacent active regions to be minimized and thus allows integrated circuits with high device packing densities to be fabricated.
Unfortunately, the conductive and dielectric layers formed on the semiconductor substrate during the integrated circuit fabrication process cannot be uniformly polished with current polishing equipment and polishing processes. One of the main reasons for this is that the polishing rate near the edge of the semiconductor substrate is often much higher than that near the center of the semiconductor substrate. Thus, portions of the conductive and dielectric layers which lie near the edge of the semiconductor substrate are often over-polished, and therefore semiconductor die located near the edge of the semiconductor substrate are lost. These die represent a substantial revenue loss to integrated circuit manufactures.
Accordingly, a need exists for a polishing process and polishing apparatus that can polish semiconductor substrates with improved center to edge uniformity.